[rescue] Screw (software) emulators!

[rescue at sunhelp.org]

On Mon, 6 Aug 2001, Ken Hansen wrote:

> I *love* it - I wonder how the speed compares to the original, and I wonder
> if it would bepossible for him to market such a "clean room" copy?

It's clocked at 8MHz, so if he kept the cycle times reasonable (haven't
looked at his VHDL in detail) it should be one of the zippiest -8's.
Marketing it would almost certainly be possible as it doesn't look like
anything proprietary was infringed upon.

> Could one fothe more knowledgeable folks out there explain for us "regular
> folk" how hard it is to emulate a complete system (CPU, etc) in a FPGA
> (Field Programmable Gate Array)? It seems very rough, but then again,
> someone appraching the "problem" of building a PDP-8 with the benefit of
> modern tools has a distinct advantade over the original designers...

It's easier than designing a new CPU in silicon.  Depending on how low
level you get, it can be as easy as writing a software emulator.  Banging
out raw VHDL frequently takes more work but can give you a faster, tighter
finished product.

He could have combined the CPU, IOU and SRAM into a larger FPGA if he had
wanted to.  There are plusses and minuses to this, but it would have made
the board much simpler physically.  2-layer PCB's do not mean that
through-hole makes more sense.  Surface mount would have worked fine for
this application and enabled the use of a larger chip.

Since the RAM can be clocked much higher than 8MHz, a shared-memory SMP
PDP-8 could be built fairly easily by clocking the RAM accesses faster and
interleaving requests from each CPU.

-James