SM100 modules (was Re: [rescue] SS10/20 death)

[dowdy at cs.colorado.edu]

Someone may have already said this...

Regarding the SM100 cpu:

The SM100 was a stop-gap processor built for the Galaxy class servers
(SPARCsystem 600) when it become clear that Texas Instruments was having
yield problems with the first SuperSPARC processors originally designed as
the base cpu for the SS600.  Sun was running late in shipping these systems
and promised to upgrade the early SM100 boxes to SuperSPARC processors in
order to honor purchase agreements/shipping commitments.

Sun asked ROSS/Cypress to "slap something together".  Basically, the SM100
is a dual SPARC2 on a card using the same RT605 (CY605) cpu at 40MHz, just
like the SS2.  They had 64KB of L2 cache, iirc, just like the SS2.  Only
difference was there were 2 cpus on the card and some cache logic.

I believe you need a version 8 SM100 to successfully utilize 2 cards (4 cpus).

They're nothing spectacular, don't utilize any spiffgnarlica cool
technology, but, they don't really "suck" anymore than a SPARC 2 or an
SS10 with a singular SM30 module does.  Not that i'd want to run one
anymore.

(As a sidenote:  Solbourne's Series6 KBus cpu boards have an MBus
connector on them even though it's not used (and no Mbus cache
coherency logic was used) because they had a single (or a few) SuperSPARC
module in the early days they'd have to move from board to board to test
while they waited on the modules to start appearing from TI.)

--stephen
--
Stephen Dowdy - Systems Administrator - CS Dept - Univ of Colorado at Boulder
dowdy at cs.colorado.edu  --  http://www.cs.colorado.edu/~dowdy/signature.html