[rescue] SS5 mobo

[Janet L. Campbell]

On Tue, 2 Mar 2004, Dave McGuire wrote:

>    I must be misremembering the internal architecture of the SS5 then, 
> and if that's the case, I stand corrected.  Does the operating system 
> not "see" an Mbus from its perspective on an SS5?  (I don't have one 
> handy at the moment)

No, there's no Mbus visible at all.

The microSparc and TurboSparc CPUs incorporate the IU, FPU, SRMMU, first
level cache, memory controller and Sbus controller all onto one chip.  
The TurboSparc also has a second level cache external to the chip.  
Nearly everything that attaches to the CPU hooks in through either the 
memory bus (RAM, the AFX slot) or the Sbus (parallel/SCSI/ethernet/...).

The SuperSparc and HyperSparc CPUs have the memory controller and Mbus to 
Sbus interface on the mainboard, not on the CPU modules.  The Mbus was 
needed as an abstraction layer to allow multiple CPU transactions to be 
handled cleanly and to deal with cache coherence.

The microSparc/TurboSparc memory access latency is a lot lower because the
overhead of the Mbus glue isn't there.  Memory transactions also don't 
have to fight for bus space with Sbus transactions, so they can be issued 
immediately.  This gave the SS4/SS5 the lowest memory latency of any 
pre-Ultra.

-Janet [just another hardware hacker]