[rescue] Loading FCode via RARPD/TFTP

[Malte Dehling]

On Tue, Jun 22, 2021 at 04:16:19PM +0200, Romain Dolbeau wrote:
> Le mar. 22 juin 2021 C  15:25, Malte Dehling <mdehling at gmail.com> a C)crit
:
> > Nice!  I wasn't aware, that might have saved me some time with my work
> > on the SPARCstation LX, too:
>
> Written quite a while ago and put on GitHub following a discussion on
> a ML, can't remember if it was 'rescue' or some other...
>
> > I'll have a closer look at your code :-)
>
> And me at yours :-)

I have added a Photo of my LX running Solaris at 1600x1200x60 VESA mode
using the 162MHz frequency I added to the FCode to the github repo:
https://github.com/1k5/sslx-vesa-mod
(scroll down in the readme)

I'm pretty happy with the results :-)

and I've now added the forth code for the cg14 / SX (from the 2.25/2.25r
OBP, they're the same) at
https://github.com/1k5/cg14-vesa-mod

It looks like the cg14 uses the same ics1562 as the cg6, at least the
register values used to set up the timings are the same (they appear in
reverse order and shifted by 4 bits in the source.)  So it should be
easy enough to add new frequencies for the cg14 like several people have
already done for the cg6.

Is there any documentation on the cg14 at all?  Just curious, I would
like to understand better how it works.

Oh, and maybe someone here knows: the 2.25r PROM is the same for the
SS10 and SS20 if I'm not mistaken.  Are the SUN 2.25 PROMs the same for
both machines, too?  They use different Part numbers I think.

> Though one of my daydream would be to add a HDMI output to the FPGA
> project and get an easier-to-display 24-bits framebuffer. And maybe
> someday there will be a working OSH GPU to add to it:-)
> Sounds far-fetched, but even 2-3 years ago it would have been
> inconceivable for someone with no hardware design experience to
> interface a crypto accelerator or a read-only sdcard to a 25+ years
> old workstation, let alone a(n almost) working USB 1.1 controller.
> FPGAs have become much more capable at a really low price-point and
> OSH is much more mature, so there is a lot more stuff to leverage for
> such 'crazy' projects.
>
> Also, Covid forced many of us into finding new hobbies :-)
>
> Though I still don't have the PCB design skills for the HDMI - even
> the sd-card a bit dodgy in my case. And getting it professionally
> designed (with the FPGA, Flash + programmer for the bitstream,
> on-board memory, support stuff for USB / micro-sd / HDMI / ..., etc.)
> would be stupidly expensive. If anyone reading this is a good PCB
> designer and is interested in helping, please let me know :-)

I wish I had these skills...


> > I hope I get around to trying your project soon, it looks very
> > impressive!  But you are right, it is a bit overkill for my current
> > needs ;-)
>
> Currently I'm rewriting the VHDL code in 'Migen' trying to bridge the
> hardware SBus with a Wishbone bus so I can benefit from all the
> available Wishbone ecosystem out there.
> Primary goal is to leverage an OHCI USB controller written in
> SpinalHDL that was integrated in the Migen-based SoC Litex.
>
> In other words, I just create an OSH system-on-chip without a CPU and
> then access its bus through the SBus. Kinda like the Fujitsu AG10-E
> was putting PCIe chips behind the SBus (never found one of those).
>
> Beware if you want to try it, getting the SBus board made isn't cheap
> in small quantities :-( Plus the specific, not-so-cheap German FPGA
> daughterboard... There's nearly 500b, worth of kit there just for a
> single FPGA and a couple carriers. And somehow I don't think a
> Kickstarter would work :-)

What makes it expensive?  I've used Aisler for a couple of projects in
the past and found their pricing to be reasonable.  At their budget rate
I think the SBUS connector might be more expensive than the board.

I've never done any FPGA work so this is probably a naive question: why
did you choose this particular board if it's so expensive?

Cheers,
Malte

--
Malte Dehling
<mdehling at gmail.com>