[rescue] SBusFPGA V1.2 status (Was: SBusFPGA update: USB Host, 256 MiB DDR3 RAM disk, ... )

[Romain Dolbeau]

Le jeu. 3 mars 2022 C  10:35, silcreval <silvercreekvalley at yahoo.com> a
ecrit :
> you've got graphic acceleration with the VexRiscv core.

It's quite basic; there's a custom layer to re-implement (some of) the cg6
hardware registers; when the console/netbsd/x11 write/read to them, it
takes the VexRiscv core out of 'reset' and the core starts executing the
microcode. The microcode looks up the registers, and then executes some C
code that re-implements the expected behavior - limited to rectangle copy
and paintings (the real hardware can do a *lot* more than that, but it's
not used by newer software...). I haven't done any measurement, but while
faster than the non-accelerated mode, it's likely slower than a real
TurboGX+. The VexRiscv core goes through the Wishbone in 32-bits chunks to
reach the SDRAM controller, and it's not designed to be super-fast.

I could switch to NaxRiscv (Vex's big out-of-order brother, which is now
booting Linux and supported in Litex) but it likely would be too big.
Instead I'm thinking about a somewhat dedicated vector engine, probably
derived from Betrusted.IO's crypto engine (of which I already use a
modified version for crypto), that would talk directly to the memory
controller in 128+bits chunk, bypassing wishbone entirely. But that's a
long(-long-long) term project to create an accelerated FB in 8/24 bits,
hopefully shareable with my other time-wasting project, NuBusFPGA (similar
to SBusFPGA but for 68k Macintoshes, because why not).

> I wonder if the GitHub could include a bit more info on the hardware side?

Not sure what you would like to see? The "sbus-to-ztex" directory contains
the full schematics & PCB for the carrier (and a zip with all the needed
files for manufacture) made with KiCad 5 (which is itself open source). The
readme has a link to the (family of) daughterboard, which is well
documented by the german manufacturer, ZTex. The only thing missing is my
custom PMod with a temperature sensor, but that's not critical (and just 2
resistors for pull-ups, 1 capacitor for decoupling, and the minuscule I2C
chip - 4-balls BGA package are *tiny*).

If you mean what is going on inside the FPGA, full source code is in
"sbus-to-ztex-gateware-migen" (minus external dependencies) in addition to
the high-level description in the readme.

Cordially,

--
Romain Dolbeau