<html><head></head><body><div class="yahoo-style-wrap" style="font-family:Arial, Helvetica, sans-serif;font-size:16px;"><div dir="ltr" data-setdir="false"><div><div dir="ltr" style="font-family: "Helvetica Neue", Helvetica, Arial, sans-serif; letter-spacing: -0.32px;" data-setdir="false">Ethan writes:</div><div dir="ltr" style="font-family: "Helvetica Neue", Helvetica, Arial, sans-serif; letter-spacing: -0.32px;" data-setdir="false"><br></div><div dir="ltr" style="font-family: "Helvetica Neue", Helvetica, Arial, sans-serif; letter-spacing: -0.32px;">>The contexts are part of the MMU+ chip, not the IU+FPU. Even then, the chip is the same in the SS2/IPX, just configured differently. I'm confident the >CPUs are interchangeable.<br></div><div dir="ltr" style="font-family: "Helvetica Neue", Helvetica, Arial, sans-serif; letter-spacing: -0.32px;"><br></div><div dir="ltr" style="font-family: "Helvetica Neue", Helvetica, Arial, sans-serif; letter-spacing: -0.32px;"><br></div></div><br></div><div dir="ltr" data-setdir="false">I have seen indications that the same SPARC Power <span>μP goes in each, the only possible gotcha is the SPARCstation 2's use of an external TI FPU. It may need to be pulled.</span></div></div></body></html>