<div dir="auto">It would be an interesting project to make a VME RAM board that uses simm/dimms.<div dir="auto"><br></div><div dir="auto">Dan.</div></div><br><div class="gmail_quote gmail_quote_container"><div dir="ltr" class="gmail_attr">On Thu, Aug 14, 2025, 11:30 Mike Spooner via rescue <<a href="mailto:rescue@sunhelp.org">rescue@sunhelp.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div><div dir="auto">There are base-address DIP switches and also configuration jumpers on the 3/1xx memory boards, that you should check.<br><br>Also, there is a P2-enable/disable jumper on the 3/160 CPU board.<br><br>Both the above are briefly covered in James Birdsall's Sun Hardware FAQ at <a href="https://www.unix-ag.uni-siegen.de/faqs/SUN-HW-FAQ.html" target="_blank" rel="noreferrer">https://www.unix-ag.uni-siegen.de/faqs/SUN-HW-FAQ.html</a><br><br>Regards,<br>Mike</div><br><br><div class="gmail_quote"><div dir="auto">On 14 August 2025 09:06:39 BST, Romain Dolbeau via rescue <<a href="mailto:rescue@sunhelp.org" target="_blank" rel="noreferrer">rescue@sunhelp.org</a>> wrote:</div><blockquote class="gmail_quote" style="margin:0pt 0pt 0pt 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
<pre><div dir="auto">Le mer. 13 août 2025 à 20:34, Alan Perry <<a href="mailto:alanp@snowmoose.com" target="_blank" rel="noreferrer">alanp@snowmoose.com</a>> a écrit :<br></div><blockquote class="gmail_quote" style="margin:0pt 0pt 1ex 0.8ex;border-left:1px solid #729fcf;padding-left:1ex"><div dir="auto">I have since found that I have a 3/160 memory board to add to the 4M on the 3/160 board I am using in the CADDStation. However it is broken and I am trying to debug it.<br></div></blockquote><div dir="auto"><br>Good luck!<br><br>You probably already found that info, but just in case...<br>The SUN 3/160 itself has some documentation on bitsavers:<br>* schematics: <<a href="https://bitsavers.org/pdf/sun/sun3/3-100/Sun-3_160_Schematic_Jun88.pdf" target="_blank" rel="noreferrer">https://bitsavers.org/pdf/sun/sun3/3-100/Sun-3_160_Schematic_Jun88.pdf</a>><br>* functionam overview:<br><<a href="https://bitsavers.org/pdf/sun/sun3/3-100/Sun-3_160_Functional_Overview.pdf" target="_blank" rel="noreferrer">https://bitsavers.org/pdf/sun/sun3/3-100/Sun-3_160_Functional_Overview.pdf</a>><br>The second one calls the CPU board 2060, which also has some documents:<br>* Hardware reference manual:<br><<a href="https://bitsavers.org/pdf/sun/sun3/3-100/800-1370-02_2060_CPU_Hardware_Reference_Manual.pdf" target="_blank" rel="noreferrer">https://bitsavers.org/pdf/sun/sun3/3-100/800-1370-02_2060_CPU_Hardware_Reference_Manual.pdf</a>><br>* Engineering manual:<br><<a href="https://bitsavers.org/pdf/sun/sun3/3-100/800-1386-13_2060_CPU_Engineering_Manual.pdf" target="_blank" rel="noreferrer">https://bitsavers.org/pdf/sun/sun3/3-100/800-1386-13_2060_CPU_Engineering_Manual.pdf</a>><br>There's also documents on how to place/configure the board in various<br>VME systems.<br><br>Unfortunately bitsavers doesn't appear to have documents pertaining to<br>the memory boards themselves.<br><br>But the CPU board documents clarify that the CPU accesses the memory<br>board via the P2 bus, an extension to VME that Sun wired on the<br>user-defined pins of the VME"s P2 connector and their own P3<br>additional connector.<br>So for the memory board and CPU board to communicate, they need to be<br>placed in appropriate slots of an appropriate VME backplane. And other<br>boards need to be placed in a way that match the requirements not just<br>of the VME bus, but also the P2 bus, to enable use of the P2 and/or<br>avoid conflicts.<br><br>Cordially,<br><br></div></pre></blockquote></div></div>_______________________________________________<br>
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