[rescue] SPARC memory query

[Jochen Kunz]

On 2002.11.28 06:49 Marc Mirza wrote:

> I would have thought synchronous memory would have far greater
> burst transfer rates..
Burst transfer rates yes, but still high latency. The question is how
high the sustrained data transfer rate for linear and random access is.
Even with modern SDRAMs you can get over 120 ns latency time (with cache
and chip set overhead) in case of cache and page miss. The DRAM cell
technic didn't get that much faster in the last years. Only the
interface type and speed has changed.

That is the reason why the latest 3 GHz P4 can't keep up with a "real"
Sun, HP 9k, RS/6k, ... in data / IO intensive load. The CPU is waiting
for data most of the time. "Real Machines" have the memory and IO
bandwith to keep the CPU bussy.
--



tsch|_,
         Jochen

Homepage: http://www.unixag-kl.fh-kl.de/~jkunz/